Dual damascene process
US6818547B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2002 |
| Grant date | Nov 16, 2004 |
| Priority date | — |
| Expiry date | Aug 27, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76877
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A dual damascene process for producing interconnects. A dielectric layer is formed over the surface of a semiconductor substrate which comprises conductive layers or MOS devices. The dielectric layer is patterned to form trench openings and a metal layer is deposited over the dielectric layer to fill the plurality of trenches. A photoresist layer is formed over the metal layer and defined to form via hole patterns above the trenches. The metal layer and the dielectric layer are etched with the patterned photoresist layer as a mask to form a plurality of via holes exposing the underlying conductive layer or MOS devices and a dual damascene opening is formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.