Architecture to suppress bit-line leakage
US6819593B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2002 |
| Grant date | Nov 16, 2004 |
| Priority date | — |
| Expiry date | Feb 26, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0425
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method to suppress bit-line leakage in a nonvolatile memory cell is achieved. The method comprises providing an array of nonvolatile memory cells comprising source and bulk terminals. The array comprises a plurality of subarrays. The sources of all the nonvolatile cells in each subarray are coupled together to form a common subarray source. Bulks of all the nonvolatile cells in the array are coupled together to form a common array bulk. A first, non-zero voltage is forced between the common subarray source and the common array bulk for a first subarray that is selected for an access operation. A second, non-zero voltage is forced between the common subarray source and the common array bulk for a second subarray that is not selected for an access operation. The second, non-zero voltage inhibits bit line leakage in the second subarray.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.