Method and system for controlling memory accesses to memory modules having a memory hub architecture
US6820181B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2002 |
| Grant date | Nov 16, 2004 |
| Priority date | — |
| Expiry date | Nov 5, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.