CMP process

US6821894B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Peter Lahnor · Dresden, DE
• Stephan Wege · Osterburken, DE

Key dates

• Filing date: Aug 20, 2001
• Grant date: Nov 23, 2004
• Expiry date: Aug 20, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/3212
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The optimization of a CMP process provides the use of an auxiliary layer (4) between a dielectric (1) in the vicinity of patterned portions and a layer of a liner (2). If the liner (2) is perforated in the CMP process, then the undercutting of the liner (2) by the chemical removal of the auxiliary layer (4) simplifies the process overall. Advantages are significantly lower defect densities due to CMP scratches, fewer short circuits, fewer alignment errors.