Semiconductor package having more reliable electrical conductive patterns
US6822323B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2003 |
| Grant date | Nov 23, 2004 |
| Priority date | — |
| Expiry date | May 12, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package has a substrate comprising a resin layer of an approximate planar plate, a die pad coupled at a top surface of a center area of the resin layer and having a printed photo imaging type protective layer thereon and a plurality of electrically conductive patterns, on which the photo imaging type protective layer and a thermosetting protective layer are printed in a consecutive order, formed at a periphery of the die pad. A semiconductor die is coupled to the photo imaging type protective layer on the die pad of the substrate by an adhesive. A plurality of conductive wires is used for electrically connecting the semiconductor die to the electrically conductive patterns. An encapsulant is used for covering the semiconductor die, the conductive wires and the surface of thermosetting protective layer on the electrically conductive patterns in order to protect them from the external environment. A plurality of contacts are coupled to the electrically conductive patterns of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.