Wafer-level package with a cavity and fabricating method thereof
US6822324B2 · kind B2 · utility
31Cited by
10References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2003 |
| Grant date | Nov 23, 2004 |
| Priority date | — |
| Expiry date | Jan 28, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16235
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer-level package with a cavity includes a chip, a substrate, and a seal member. The chip has a micro device and a plurality of bonding pads electrically connected to the micro device. The substrate has a plurality of through conductive vias corresponding and electrically connected to the bonding pads. Each of the bonding pads on the chip is provided with a conductive bump for electrically connecting the bonding pad to the conductive via. The seal member surrounds the package to form a hermetical cavity. The present invention further provides a method for fabricating the wafer-level package with a cavity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.