Method for forming a MIM capacitor
US6825080B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2003 |
| Grant date | Nov 30, 2004 |
| Priority date | — |
| Expiry date | Oct 2, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76838
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a MIM capacitor which is characterized as follows. We provide a semiconductor structure having a first region and a capacitor region. Next we form a first conductive layer over the semiconductor structure. The first conductive layer is patterned to form a plurality of trenches in the capacitor region. We form a capacitor dielectric layer over the first conductive layer. We form a top plate over the capacitor dielectric layer in the capacitor region. The first conductive layer in the first region is patterned to form conductive patterns and a bottom plate. An interlevel dielectric layer is formed over the first conductive layer and top plate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.