Stress inducing spacers

US6825529B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Dureseti Chidambarrao · Weston, US
• Omer H. Dokumaci · Wappingers Falls, US
• Bruce B. Doris · Brewster, US
• Jack A. Mandelman · Stormville, US
• Xavier Baie · Wavre, BE

Key dates

• Filing date: Dec 12, 2002
• Grant date: Nov 30, 2004
• Expiry date: Dec 12, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/201

Abstract

A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both the gate and the substrate and impose forces on adjacent substrate areas. Another embodiment comprises compressive stresses imposed in the plane of the channel using SOI sidewall spacers made of polysilicon that is expanded by oxidation. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance have been demonstrated.