Current mode logic (CML) circuit concept for a variable delay element

US6825707B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Hans-Heinrich Viehmann · Munich, DE
• Stefan Lammers · Hersbruck, DE

Key dates

• Filing date: Mar 10, 2003
• Grant date: Nov 30, 2004
• Expiry date: Mar 10, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K2005/00208
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

An apparatus for a current mode logic variable delay element. A preferred embodiment comprises an input signal that is provided to a multiplexer (for example, multiplexer 210) in both buffered (via a buffer (for example, buffer 205)) and unbuffered form. A control signal of the multiplexer may be used to select from either the buffered or unbuffered input signals. By using a control signal at an intermediate value (somewhere in between values that selects the buffered or unbuffered input signals), the multiplexer may then combine the buffered and unbuffered input signals in proportion with the value of the control signal and imparts a delay upon the input signal that may be in between the delay imparted by the buffer.