Patent · US Expired

On chip scrambling

US6826111B2 · kind B2 · utility

18Cited by

4References

21Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Ralf Schneider · Birkenfeld, DE
Evangelos Stavrou · Munich, DE
Tobias Hartner · Munich, DE
Norbert Wirth · Unterschleißheim, DE

Key dates

Filing date	Jun 28, 2002
Grant date	Nov 30, 2004
Priority date	—
Expiry date	Dec 11, 2022

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/18
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method includes providing a semiconductor memory device having at least one memory cell array. The memory cell array has a multiplicity of memory cells arranged in a matrix-like manner. Each of the memory cells is assigned a physical address and an electrical address. The method also includes inputting a physical address of a memory cell that is to be addressed into an address input device of the semiconductor memory device, decoding the input physical address into the assigned electrical address of the memory cell to be addressed by an address decoder device of the semiconductor memory device, and outputting the electrical address to the memory cell array in order to address the memory cell.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.