CMOS of semiconductor device and method for manufacturing the same
US6828185B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2002 |
| Grant date | Dec 7, 2004 |
| Priority date | — |
| Expiry date | Sep 18, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0181
Abstract
The present invention discloses the single gate CMOS with the surface channel manufactured according to the manufacturing method of the present invention is very advantageous for improving the characteristics, yield and reliability of the device, by performing decoupled plasma nitridation (DPN) process on the gate oxide film of the cell NMOS and the peripheral PMOS, respectively, thereby forming a silicon nitride on the surface of the gate oxide film. Further, the single gate CMOS with the surface channel can be formed more easily through the simplified process in overall, without requiring a separate transient ion implantation process, even when the gate electrode of the n+ polysilicon layer is used, by having the threshold voltage of the cell NMOS be approximately +0.9V, the threshold voltage of the peripheral PMOS be approximately −0.5V and above, and the threshold voltage of the peripheral NMOS be approximately +0.5V and below. In addition, since the cell NMOS already has +0.9V of threshold voltage, back bias does not have to be applied separately to achieve the +0.9V threshold voltage, and the device with low power consumption is formed successfully.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.