Method of manufacturing multi-level contacts by sizing of contact sizes in integrated circuits
US6828240B2 · kind B2 · utility
7Cited by
8References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2002 |
| Grant date | Dec 7, 2004 |
| Priority date | — |
| Expiry date | Apr 5, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76816
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming an integrated circuit includes etching a first opening to a first depth in a dielectric material over a semiconductor device on a first semiconductor substrate and etching a second opening to a second depth in the dielectric material over the first semiconductor substrate. The first and second openings are differently sized to respectively etch to the first and second depths in about the same time due to etch lag. The first and second openings are filled with conductive material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.