Vertical nanotube transistor and process for fabricating the same
US6830981B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2002 |
| Grant date | Dec 14, 2004 |
| Priority date | — |
| Expiry date | Feb 20, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/845
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A vertical nanotube transistor and a process for fabricating the same. First, a source layer and a catalyst layer are successively formed on a substrate. A dielectric layer is formed on the catalyst layer and the substrate. Next, the dielectric layer is selectively removed to form a first dielectric mesa, a gate dielectric layer spaced apart from the first dielectric mesa by a first opening, and a second dielectric mesa spaced apart from the gate dielectric layer by a second opening. Next, a nanotube layer is formed in the first opening. Finally, a drain layer is formed on the nanotube layer and the first dielectric mesa, and a gate layer is formed in the second opening. The formation position of the nanotubes can be precisely controlled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.