Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
US6831292B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2002 |
| Grant date | Dec 14, 2004 |
| Priority date | — |
| Expiry date | Jan 22, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/926
Abstract
Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.