Integrated circuit having multiple memory types and method of formation
US6831310B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2003 |
| Grant date | Dec 14, 2004 |
| Priority date | — |
| Expiry date | Nov 10, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A transistor (10) is formed having three separately controllable gates (44, 42, 18). The three gate regions may be electrically biased differently and the gate regions may have different conductivity properties. The dielectrics on the channel sidewall may be different than the dielectrics on the top of the channel. Electrical contacts to source, drain and the three gates is selectively made. By including charge storage layers, such as nanoclusters, adjacent the transistor channel and controlling the charge storage layers via the three gate regions, both volatile and non-volatile memory cells are realized using the same process to create a universal memory process. When implemented as a volatile cell, the height of the transistor and the characteristics of channel sidewall dielectrics control the memory retention characteristics. When implemented as a nonvolatile cell, the width of the transistor and the characteristics of the overlying channel dielectrics control the memory retention characteristics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.