Memory cell configuration for a DRAM memory with a contact bit terminal for two trench capacitors of different rows

US6831320B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventor

• Peter Beer · Waldshut-Tiengen, DE

Key dates

• Filing date: Sep 30, 2003
• Grant date: Dec 14, 2004
• Expiry date: Sep 30, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/485

Abstract

A memory cell configuration connects two trench capacitors to a bit line through a contact bit terminal. Trench capacitors are disposed in a regular grid. Word and bit lines are disposed in a mutually perpendicular crossover structure. An active region in which a selection transistor of an adjoining trench capacitor is introduced is disposed respectively between two trench capacitors of a row. Trench capacitors of two rows are laterally offset with respect to one another. Two active regions of adjacent rows are electrically connected to one another through a connecting line. Connected active regions form a common terminal region connected to a contact bit terminal, which is connected to a bit line. Bit lines are disposed between rows of trench capacitors and parallel thereto. By reducing the contact bit terminals, capacitances of the bit lines are reduced and interference signal transmission between word line and contact bit terminals is reduced.