System for semiconductor package with stacked dies
US6833287B1 · kind B1 · utility
30Cited by
12References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2003 |
| Grant date | Dec 21, 2004 |
| Priority date | — |
| Expiry date | Jun 16, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package with stacked dies and method of assembly is provided. A first die is attached to a substrate. A protective layer is placed on the first die over a central area thereof. The first die is electrically connected to the substrate. An intermediate adhesive layer is applied over the protective layer. A second die is attached to the intermediate adhesive layer and electrically connected to the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.