Inventor · Singapore, SG

Zigmund Ramirez Camacho

220Patents

17h-index

46Co-inventors

82Inventor score

Filing activity: Jun 16, 2003 → Oct 9, 2020

Most-cited inventions

Patent	Title	Area	Cited by	Status
US8420447B2	Integrated circuit packaging system with flipchip leadframe and method of manufacture thereof	Electricity	267	Active
US7517733B2	Leadframe design for QFN package with top terminal leads	Electricity	115	Active
US7915716B2	Integrated circuit package system with leadframe array	Electricity	60	Active
US8409922B2	Semiconductor device and method of forming leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect	Electricity	54	Active
US8993376B2	Semiconductor device and method of forming wafer-level multi-row etched leadframe with base leads and embedded semiconductor die	Electricity	49	Active
US8021907B2	Method and apparatus for thermally enhanced semiconductor package	Electricity	42	Active
US9006031B2	Semiconductor device and method of forming EWLB package with standoff conductive layer over encapsulant bumps	Electricity	41	Active
US9177832B2	Semiconductor device and method of forming a reconfigured stackable wafer level package with vertical interconnect	Electricity	40	Active
US8940636B2	Through hole vias at saw streets including protrusions or recesses for interconnection	Electricity	39	Active
US7977579B2	Multiple flip-chip integrated circuit package system	Emerging Cross-Sectional Technologies	36	Expired
US6833287B1	System for semiconductor package with stacked dies	Electricity	30	Expired
US7400049B2	Integrated circuit package system with heat sink	Electricity	27	Expired
US7851246B2	Semiconductor device with optical sensor and method of forming interconnect structure on front and backside of the device	Electricity	25	Active
US8076184B1	Semiconductor device and method of forming wafer-level multi-row etched leadframe with base leads and embedded semiconductor die	Electricity	24	Active
US8035207B2	Stackable integrated circuit package system with recess	Electricity	20	Active
US7868471B2	Integrated circuit package-in-package system with leads	Electricity	19	Active
US7964450B2	Wirebondless wafer level package with plated bumps and interconnects	Electricity	17	Active
US8241956B2	Semiconductor device and method of forming wafer level multi-row etched lead package	Electricity	16	Active
US9330994B2	Semiconductor device and method of forming RDL and vertical interconnect by laser direct structuring	Electricity	16	Active
US7691674B1	Integrated circuit packaging system with stacked device and method of manufacturing thereof	Electricity	15	Active
US7888181B2	Method of forming a wafer level package with RDL interconnection over encapsulant between bump and semiconductor die	Electricity	15	Active
US8884418B2	Semiconductor device and method of forming PIP with inner known good die interconnected with conductive bumps	Electricity	13	Active
US8106499B2	Integrated circuit packaging system with a dual substrate package and method of manufacture thereof	Electricity	13	Active
US7838395B2	Semiconductor wafer level interconnect package utilizing conductive ring and pad for separate voltage supplies and method of making the same	Electricity	13	Active
US7790576B2	Semiconductor device and method of forming through hole vias in die extension region around periphery of die	Electricity	12	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.