Thin profile semiconductor package which reduces warpage and damage during laser markings
US6833619B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2003 |
| Grant date | Dec 21, 2004 |
| Priority date | — |
| Expiry date | Apr 28, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package has a substrate comprising a resin layer of an approximate planar plate, a cavity passing through the resin layer vertically at a center area thereof, a plurality of electrically conductive patterns formed at a bottom surface of the resin layer, and a conductive plan. An adhesive layer of a predetermined thickness is formed at an upper part of an inside of the cavity. A semiconductor die is positioned inside the cavity of the substrate and has a plurality of bond pads formed at a bottom surface thereof, a bottom surface of the adhesive layer being bonded to a top surface thereof. A plurality of conductive wires for electrically connecting the bond pads of the semiconductor die to the electrically conductive patterns are formed at a bottom surface of the substrate. An encapsulant is used for covering the semiconductor die formed at the lower part of the adhesive layer, the conductive wires and the cavity. A plurality of solder balls are fused to the electrically conductive patterns, which is formed at the bottom surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.