Multichip package
US6833993B2 · kind B2 · utility
16Cited by
11References
29Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 3, 2003 |
| Grant date | Dec 21, 2004 |
| Priority date | — |
| Expiry date | Jun 26, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multichip package mainly includes a substrate, a first chip disposed on the lower surface of the substrate by flip-chip bonding, at least one second chip and a heat spreader disposed on the upper surface of the substrate. A plurality of solder balls are formed at the periphery of the first chip on the lower surface of the substrate wherein the solder balls electrically connected to the first chip or the second chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.