Isolation device over field in a memory device
US6834019B2 · kind B2 · utility
13Cited by
21References
66Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2002 |
| Grant date | Dec 21, 2004 |
| Priority date | — |
| Expiry date | Nov 11, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/906
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes isolation devices located between memory cells. A plurality of isolation lines connects the isolation devices to a positive voltage during normal operations but still keeps the isolation devices in the off state to provide isolation between the memory cells. A current control circuit is placed between the isolation lines and a power node for reducing a current flowing between the isolation lines and the power node in case a deflect occurs at any one of isolation devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.