Method and arrangement for frequency doubling

US6836162B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Edoardo Prete · Birkenfeld, DE
• David Müller · Mannheim, DE

Key dates

• Filing date: Apr 30, 2003
• Grant date: Dec 28, 2004
• Expiry date: Apr 30, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03B19/14
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

To generate an output signal (11) the frequency of which is twice the frequency of an input signal (1, 2), a delayed signal (3, 4) which is delayed relative to the input signal (1, 2) by a quarter of the latter's cycle period is generated and the output signal (11) is then generated as the difference between the rectified input signal (1, 2) and the rectified delayed signal (3, 4). The input signal (1, 2) and the delayed signal (3, 4) are advantageously rectified by using differential signals each comprising a positive component signal (1, 3) and a negative component signal (2, 4). A respective one of two transistors connected in parallel is driven by a positive component signal (1, 3) and a negative component signal (2, 4) in such a way that a positive half-wave causes the relevant transistor (5-8) to conduct and the relevant transistor (5-8) blocks in a negative half-wave. The rectified input signal (1, 2) or delayed signal (3, 4) is obtained from the two component currents flowing through the pairs of transistors (5-8) connected in parallel when the currents are added. The rectified input signal (1, 2) and delayed signal (3, 4), which are in the form of current signals, can be p…