Independent sequencers in a DRAM control structure
US6836831B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2002 |
| Grant date | Dec 28, 2004 |
| Priority date | — |
| Expiry date | Apr 17, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1647
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus in a computer system are disclosed for providing a memory controller featuring a dedicated bank sequencer for each memory bank in a memory system. Each bank sequencer controls the dispatch of load and store requests to a central controller such that each request sent to the central controller can be served by the associated memory bank at the time that the central controller receives the request. Since every request received by the central controller is valid from a bank timing standpoint, the central controller is free to process the requests from a predetermined priority basis, without concern for bank availability. This significantly improves the design of the memory controller in the processing system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.