High-speed algorithmic pattern generator
US6836868B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2000 |
| Grant date | Dec 28, 2004 |
| Priority date | — |
| Expiry date | Sep 13, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/24
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An algorithmic pattern generator for generating an output vector on each pulse of a clock signal includes a vector memory for storing a vector and an accompanying repeat number at each of several addresses. On each of N consecutive clock signal pulses, a repeat processor appends an instance of a vector read out of the vector memory to the pattern generator's output vector sequence. An instruction processor causes the instruction memory to read out instructions and responds to each instruction by telling the instruction processor to signal the address counter to supply the starting address to the vector memory and to thereafter periodically increment the starting address for M consecutive clock signal cycles. When appending N instances of each vector to the pattern generator output sequence, the repeat processor inhibits the address counter from incrementing its output address for N−1 cock signal cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.