Method for reducing line edge roughness of oxide material using chemical oxide removal

US6838347B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Joyce C. Liu · Carmel, US
• Wesley C. Natzle · New Paltz, US
• Richard S. Wise · Beacon, US
• Hongwen Yan · Somers, US
• Bidan Zhang · Beekman, US

Key dates

• Filing date: Sep 23, 2003
• Grant date: Jan 4, 2005
• Expiry date: Sep 23, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/31116
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for reducing line edge roughness (LER) of a semiconductor gate structure includes patterning a photoresist layer formed over an oxide hardmask layer. The photoresist layer is etched so as to transfer a photoresist pattern to the oxide hardmask layer, the photoresist pattern having an initial LER. The exposed surfaces of the oxide hardmask are etched with a chemical oxide removal (COR) so as to form a reaction product on the exposed surfaces, wherein concave portions of the exposed surfaces are etched at a reduced rate with respect to convex portions of the exposed surfaces.