CMOS device structure with improved PFET gate electrode

US6838695B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Bruce B. Doris · Brewster, US
• Ashima B. Chakravarti · Hopewell Junction, US
• Kevin K. Chan · Staten Island, US
• Daniel A. Uriarte · Wappingers Falls, US

Key dates

• Filing date: Nov 25, 2002
• Grant date: Jan 4, 2005
• Expiry date: Jan 10, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor device structure includes a substrate, a dielectric layer disposed on the substrate, first and second stacks disposed on the dielectric layer. The first stack includes a first silicon layer disposed on the dielectric layer, a silicon germanium layer disposed on the first silicon layer, a second silicon layer disposed on the silicon germanium layer, and a third silicon layer disposed on the second silicon layer. The second stack includes a first silicon layer disposed on the dielectric layer, and a second silicon layer disposed on the first silicon layer. Alternatively, the silicon germanium layer includes Boron.