Trench FET with non overlapping poly and remote contact therefor
US6838735B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2000 |
| Grant date | Jan 4, 2005 |
| Priority date | — |
| Expiry date | Feb 24, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/519
Abstract
A power MOSFET has a plurality of spaced rows of parallel coextensive trenches. The trenches are lined with a gate oxide and are filled with conductive polysilicon. Spaced narrow polysilicon strips overlie the silicon surface and connects adjacent trenches to one another. The source contact is made at a location remote from the trenches and between the rows of trenches. The trenches are 1.8 microns deep, are 0.6 microns wide and are spaced by about 0.6 microns or greater. The device has a very low figure of merit and is useful especially in low voltage circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.