Memory module with offset data lines and bit line swizzle configuration

US6839266B1 · kind B1 · utility

Assignee

• Rambus Inc. · US

Inventors

• Billy Wayne Garrett, Jr. · Mountain View, US
• Frederick A. Ware · Los Altos Hills, US
• Craig E. Hampel · San Jose, US
• Richard M. Barth · Palo Alto, US
• Don Stark · Palo Alto, US
• Abhijit M. Abhyankar · Sunnyvale, US
• Catherine Chen · Cupertino, US
• Thomas J. Sheffler · San Francisco, US
• Ely Tsern · Los Altos, US
• Steven C. Woo · Saratoga, US

Key dates

• Filing date: Mar 20, 2002
• Grant date: Jan 4, 2005
• Expiry date: Jan 25, 2023

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C7/1072
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A memory module includes an array of N memory devices, each memory device having M data pins, where N is greater than M, and M and N are positive integers; and N bit lines traversing the array of N memory devices, such that each one of the N bit lines is connected to M of the N memory devices.