Apparatus and method for parallel programming of antifuses
US6839292B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2001 |
| Grant date | Jan 4, 2005 |
| Priority date | — |
| Expiry date | Jan 22, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for programming programmable elements of a plurality of memory devices in parallel. Each of the memory devices include an address latch for latching an address corresponding to a programmable element to be programmed and logic circuitry for receiving address load commands. The logic circuitry provides control signals to the address latch in response to receiving the load commands to cause the address latch to latch an corresponding to a programmable element to be programmed. By using the address latch and logic circuitry, the programming of a programmable element of a first memory device and the programming the second programmable element of a second memory device can occur in parallel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.