Patent · US Expired

Circuit configuration for generating control signals for testing high-frequency synchronous digital circuits

US6839397B2 · kind B2 · utility

1Cited by

2References

11Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Wolfgang Ernst · Munich, DE
Gunnar Krause · Munich, DE
Justus Kuhn · Birkenfeld, DE
Jens Lüpke · Hersbruck, DE
Jochen Müller · Hersbruck, DE
Peter Pöchmüller · Birkenfeld, DE
Michael Schittenhelm · Poing, DE

Key dates

Filing date	Jul 18, 2001
Grant date	Jan 4, 2005
Priority date	—
Expiry date	Jun 26, 2023

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/14
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A circuit configuration for generating control signals for testing high-frequency synchronous digital circuits, especially memory chips, is described. A p-stage shift register which is clocked at a clock frequency corresponding to the high clock frequency of the digital circuit to be tested has connected to its parallel loading inputs p logical gates which logically combine a static control word with a dynamic n-position test word. The combined logical value is loaded into the shift register at a low-frequency loading clock rate so that a control signal, the value of which depends on the information loaded into the shift register in each clock cycle of the clock frequency of the latter is generated at the serial output of the shift register.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.