Etching process for a two-layer metallization

US6841481B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Gabriela Brase · Fishkill, US
• Gregoire Grandremy · Dresden, DE

Key dates

• Filing date: Feb 11, 2002
• Grant date: Jan 11, 2005
• Expiry date: Jun 3, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76807
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The novel etching process for a two-layer metallization, or dual damascene patterning, is simple and cost-effective to carry out and reliably prevents fences from forming during the etching process in the region of the polymer intermediate layer. The etching of the oxide layer and of the polymer intermediate layer for the dual damascene patterning is effected by a CF4 ARC open process with high selectivity with respect to the photoresist with a lengthened etching time.