Fully-depleted SOI MOSFETs with low source and drain resistance and minimal overlap capacitance using a recessed channel damascene gate process

US6841831B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Hussein I. Hanafi · Berkeley Heights, US
• Diane C. Boyd · Lagrangeville, US
• Kevin K. Chan · Staten Island, US
• Wesley C. Natzle · New Paltz, US
• Leathen Shi · Yorktown Heights, US

Key dates

• Filing date: Jun 13, 2003
• Grant date: Jan 11, 2005
• Expiry date: Jun 13, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/027

Abstract

A sub-0.05 μm channel length fully-depleted SOI MOSFET device having low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. The sub-0.05 μm channel length fully-depleted SOI MOSFET device includes an SOI structure which contains at least an SOI layer having a channel region of a first thickness and abutting source/drain regions of a second thickness present therein, wherein the second thickness is greater than the first thickness and the source/drain regions having a salicide layer present thereon. A gate region is present also atop the SOI layer.