Method for determining the leakage power for an integrated circuit
US6842714B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2003 |
| Grant date | Jan 11, 2005 |
| Priority date | — |
| Expiry date | Aug 22, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3008
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for determining full chip leakage power first estimates leakage power and dynamic power for each circuit macro. The power supply voltage to each macro is first assumed to be nominal. The power dissipation for each macro is modeled as a current source whose value is the estimated power divided by the nominal power supply voltage. The power distribution network is modeled as a resistive grids. The thermal environment of the IC and its electronic package are modeled as multi dimensional grids of thermal elements. Algebraic multi-grid (AMG) methods are used to calculate updated circuit macro voltages and temperatures. The macro voltages and temperatures are updated and updated leakage and dynamic power dissipation are calculated. Iterations are continued until leakage power converges to a final value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.