Method of forming DRAM access transistors
US6844591B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 17, 2003 |
| Grant date | Jan 18, 2005 |
| Priority date | — |
| Expiry date | Sep 17, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
Abstract
Self-aligned recessed gate structures and method of formation are disclosed. Field oxide areas for isolation are first formed in a semiconductor substrate. A plurality of columns are defined in an insulating layer formed over the semiconductor substrate subsequent to which a thin sacrificial oxide layer is formed over exposed regions of the semiconductor substrate but not over the field oxide areas. A dielectric material is then provided on sidewalls of each column and over portions of the sacrificial oxide layer and of the field oxide areas. A first etch is conducted to form a first set of trenches within the semiconductor substrate and a plurality of recesses within the field oxide areas. A second etch is conducted to remove dielectric residue remaining on the sidewalls of the columns and to form a second set of trenches. Polysilicon is then deposited within the second set of trenches and within the recesses to form recessed conductive gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.