Zero power chip standby mode
US6845054B2 · kind B2 · utility
7Cited by
25References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2002 |
| Grant date | Jan 18, 2005 |
| Priority date | — |
| Expiry date | Aug 28, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/141
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A zero power standby mode in a memory device used in a system, such as a battery powered hand held device. By disconnecting the internal power supply bus on the memory device from the external power supply during standby mode, the junction leakage and gate induced drain leakage can be eliminated to achieve a true zero-power standby mode. A p-channel field effect transistor (FET) may be used to gate the external power supply such that the internal power supply bus on the memory device may be disconnected from the external power supply.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.