Interpage prologue to protect virtual address mappings
US6845353B1 · kind B1 · utility
10Cited by
10References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1999 |
| Grant date | Jan 18, 2005 |
| Priority date | — |
| Expiry date | Dec 23, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3017
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a computer which translates instructions from a target instruction set to a host instruction set, a method for determining validity of a translation of a target instruction linked to an earlier translation including the steps of testing a memory address of a target instruction to be executed against a copy of the memory address of the target instruction from which a translation of the target instruction was made, executing the translation if the addresses compare, and generating an exception if the addresses do not compare.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.