System and method to provide tight locking for DLL and PLL with large range, and dynamic tracking of PVT variations using interleaved delay lines
US6845459B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 9, 2003 |
| Grant date | Jan 18, 2005 |
| Priority date | — |
| Expiry date | Dec 9, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0998
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and voltage (PVT) variations while a second portion, in series with the first portion, provides a variable amount of delay that substantially tracks changes in process, temperature, and voltage variations. By combining, or interleaving, the two types of delay, single and dual locked loops constructed using the present invention achieve a desired jitter performance under PVT variations, dynamically track the delay variations of one coarse tap without a large number of delay taps, and provide for quick and tight locking. Methods of operating delay lines and locked loops are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.