Method to reduce junction leakage current in strained silicon on silicon-germanium devices
US6846720B2 · kind B2 · utility
12Cited by
15References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2003 |
| Grant date | Jan 25, 2005 |
| Priority date | — |
| Expiry date | Jun 18, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02664
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A MOSFET device in strained silicon-on-SiGe and a method of forming the device are described. The said device achieves reduced junction leakage due to the lower band-gap values of SiGe. The method consists of forming isolation trenches in a composite strained-Si/SiGe substrate and growing a liner oxide by wet oxidation such that oxidation is selective to SiGe only, with negligible oxidation of silicon surfaces. Selective oxidation results in oxide encroachment under strained-Si, thereby reducing the junction area after device fabrication is completed. Reduced junction area leads to reduced n+/p or p+/n junction leakage current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.