Method for preventing low-k dielectric layer cracking in multi-layered dual damascene metallization layers
US6846756B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2002 |
| Grant date | Jan 25, 2005 |
| Priority date | — |
| Expiry date | Sep 4, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31127
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for plasma treatment of anisotropically etched openings to improve a crack initiation and propagation resistance including providing a semiconductor wafer having a process surface including anisotropically etched openings extending at least partially through a dielectric insulating layer; plasma treating in at least one plasma treatment the process surface including the anisotropically etched openings to improve an adhesion of a subsequently deposited refractory metal adhesion/barrier layer thereover; and, blanket depositing at least one refractory metal adhesion/barrier layer to line the anisotropically etched openings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.