Bumping technology in stacked die configurations
US6847105B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 21, 2001 |
| Grant date | Jan 25, 2005 |
| Priority date | — |
| Expiry date | Sep 22, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T83/0467
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked semiconductor package including a plurality of stacked semiconductor devices on a substrate, and a method of forming the same. The semiconductor devices are stacked in an active surface-to-backside configuration. The top semiconductor die is flipped over to face the active surface of the semiconductor die directly below. An electrical connector can extend from a bond pad on the top semiconductor die to a redistribution circuit on the semiconductor die below. The redistribution circuit can be electrically connected to a substrate. Alternatively, an electrical connector extends from a bond pad on top semiconductor die to a bond pad on a substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.