Methods for fabricating an improved floating gate memory cell

US6849501B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventor

• Paul Rudeck · Boise, US

Key dates

• Filing date: May 20, 2003
• Grant date: Feb 1, 2005
• Expiry date: May 20, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6891

Abstract

Methods for fabricating improved floating gate memory cells are provided. A substrate and a first insulating layer are fabricated, where the first insulating layer is formed on the substrate. A shallow trench isolation (STI) region is fabricated having walls that form edges in the substrate and edges to a first conducting layer where the edges of the first conducting layer are aligned with the edges of the substrate. A second insulating layer is formed on the first conducting layer and a second conducting layer formed on the first insulating layer. The invention also includes a method that capitalizes on a single step process for defining the STI region and the floating gate for a memory cell that aligns edges formed in the substrate by the walls of the STI region with the edges of the floating gate formed by the walls of the STI region.