Method of forming multiple gate insulators on a strained semiconductor heterostructure
US6849508B2 · kind B2 · utility
5Cited by
26References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2002 |
| Grant date | Feb 1, 2005 |
| Priority date | — |
| Expiry date | Jun 7, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/514
Abstract
A method is disclosed for forming multiple gate insulators on a strained semiconductor heterostructure as well as the devices and circuits formed therefrom. In an embodiment, the method includes the steps of depositing a first insulators on the strained semiconductor heterostructure, removing at least a portion of the first insulators from the strained semiconductor heterostructure, and depositing a second insulators on the strained semiconductor heterostructure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.