Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations
US6850438B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2003 |
| Grant date | Feb 1, 2005 |
| Priority date | — |
| Expiry date | Jan 24, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.