Method of trimming a gate electrode structure
US6852584B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2004 |
| Grant date | Feb 8, 2005 |
| Priority date | — |
| Expiry date | Jan 14, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32137
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and processing tool are provided for trimming a gate electrode structure containing a gate electrode layer with a first dimension. A reaction layer is formed through reaction with the gate electrode structure. The reaction layer is the selectively removed from the unreacted portion of the gate electrode structure by chemical etching, thereby forming a trimmed gate electrode structure with a second dimension that is smaller than the first dimension. The trimming process can be carried out under process conditions where formation of the reaction layer is substantially self-limiting. The trimming process can be repeated to further reduce the dimension of the gate electrode structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.