Wafer level package having a side package
US6852607B2 · kind B2 · utility
36Cited by
2References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 10, 2002 |
| Grant date | Feb 8, 2005 |
| Priority date | — |
| Expiry date | May 10, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a wafer level package includes forming a semiconductor wafer including semiconductor chips, and forming a package body on the sides of each semiconductor chip. The package body is formed by forming a space between each semiconductor chip and potting a package material in the space, which can be a mold resin. The wafer is then separated into separate semiconductor chips by cutting through the package body.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.