Level-shifting circuitry having “high” output impedance during disable mode
US6853233B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2000 |
| Grant date | Feb 8, 2005 |
| Priority date | — |
| Expiry date | Sep 13, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09429
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level shifting circuit includes a level-shifting section responsive to an input logic signal, which varies between a first voltage level (e.g., ground) and a second voltage level (e.g., 2.1 V). The level-shifting section provides an output logic signal at an output terminal. The output logic signal varies between the first voltage level and a third voltage level (e.g., 2.5V). The circuit also includes an enable/disable section with a first portion coupled between the level shifting section and a first reference voltage node (e.g., ground) and a second portion coupled between the level shifting section and the third reference voltage node. The enable/disable section causes the output terminal to be placed at a relatively high output impedance condition independent of the logic state of the input logic signal in response to a disable mode indication from an enable/disable signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.