Flash memory cell including two floating gates and an erasing gate
US6855598B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2003 |
| Grant date | Feb 15, 2005 |
| Priority date | — |
| Expiry date | Apr 7, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A flash memory includes a substrate, at least a source and two drains formed in the substrate, and the source located between the drains, two tunnel oxide layers formed on the substrate between each drain and the source, a floating gate formed on each of the tunnel oxide layers, a plurality of first oxide layers formed aside each of the floating gates, a dielectric layer formed on each of the floating gates, a control gate formed on each of the dielectric layers, a plurality of second oxide layers formed on surfaces of the control gates and extending toward both sides of the control gates, a lateral width of each second oxide layer being larger than a lateral width of each oxide layer, a third oxide layer formed on the source, and an erasing gate formed on the third oxide layer and located between the floating gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.