Fabrication method of a flash memory device

US6855599B2 · kind B2 · utility

Assignee

• POWERCHIP SEMICONDUCTOR CORP. · TW

Inventors

• Chih-Wei Hung · Baoshan, TW
• Da Sung · Hsinchu, TW
• Chih-Ming Chen · Taipei, TW

Key dates

• Filing date: Dec 31, 2003
• Grant date: Feb 15, 2005
• Expiry date: Dec 31, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B69/00

Abstract

A flash memory device includes a substrate having a trench, a deep N-type well region in the substrate, a stacked gate structure on the substrate, a first and a second spacer on a sidewall of the stacked gate, wherein the first spacer is connected with the top of the trench, a source region in the substrate under the first spacer, a drain region in the substrate under the second spacer, a P-type well region between the stacked gate and the deep N-type well region, wherein the junction between the two well regions is higher than the bottom of the trench, a doped region along the bottom and the sidewall of the trench, wherein this doped region is connected with the source region and isolates the P-type well region from the contact formed in the trench, the contact being electrically connected to the source region.