Semiconductor nano-rod devices
US6855606B2 · kind B2 · utility
105Cited by
7References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2003 |
| Grant date | Feb 15, 2005 |
| Priority date | — |
| Expiry date | May 16, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/43
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
In a method of manufacturing a semiconductor device, a semiconductor layer is patterned to form a source region, a channel region, and a drain region in the semiconductor layer. The channel region extends between the source region and the drain region. Corners of the channel region are rounded by annealing the channel region to form a nano-rod structure. Part of the nano-rod structure is then used as a gate channel. Preferably, a gate dielectric and a gate electrode both wrap around the nano-rod structure, with the gate dielectric being between the nano-rod structure and the gate electrode, to form a transistor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.