Method of fabricating a heterojunction bipolar transistor
US6855613B1 · kind B1 · utility
10Cited by
16References
17Claims
0Family size
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Key dates
| Filing date | Nov 4, 1999 |
| Grant date | Feb 15, 2005 |
| Priority date | — |
| Expiry date | Nov 4, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/85
Abstract
A method of fabricating a III-V heterostructure semiconductor device. The method includes the steps of forming at least one conductive post overlying a semiconductor region to form a structure, encapsulating the structure and the conductive post to form a planarized cured passivation layer, and exposing the conductive post through the planarized cured passivation layer to form the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.